Vertical field effect transistor (vertical FET) is a new solution of integration in current semiconductor integrated circuit. The vertical FET is a device in which the source-drain current flows within the through hole perpendicular to the surface of the substrate. If the surface of the substrate is horizontal, the vertical FET is usually an upright through hole, of which the top and the bottom are source/drain electrode or drain/source electrode. A major advantage of the vertical FET is that the length of the through hole is not defined by photolithography, but is defined by, e.g. epitaxy or lamination, which can provide good thickness control even in nanometer scale. Another advantage is that the vertical FET is intrinsically suitable for designing asymmetric devices.
However, with regard to vertical FET devices, challenges exist for reducing parasitic resistance, and obtaining vertical FETs with different gate lengths and better isolation in a single structure.
Thus, there is a need for a technical solution to reduce the parasitic resistance of semiconductor devices of vertical FETs, provide vertical FETs with different gate lengths and better isolation in a single semiconductor structure.